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ASAHI KASEI
[AK4706]
AK4706
2ch 24bit DAC with AV Switch & HD/SD Video Filter
GENERAL DESCRIPTION The AK4706 offers the ideal features for digital set-top-box systems. Using AKM's multi-bit architecture for its modulator, the AK4706 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4706 integrates a combination of SCF and CTF filters, removing the need for high cost external filters and increasing performance for systems with excessive clock jitter. The AK4706 also including the audio switches, volumes, video switches, HD/SD video filters, etc. designed primarily for digital set-top-box systems with SCART routing. The AK4706 is offered in a space saving 64-pin LQFP package. FEATURES DAC Sampling Rates Ranging from 8kHz to 50kHz 64dB High Attenuation 8x FIR Digital Filter 2nd Order Analog LPF On Chip Buffer with Single-Ended Output Digital De-Emphasis for 32k, 44.1k and 48kHz Sampling I/F Format: 24bit MSB Justified, I2S, 18/16bit LSB Justified Master Clock: 256fs, 384fs High Tolerance to Clock Jitter Analog Switches Audio Section THD+N: -86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Stereo Analog Volume with Pop-noise Free Circuit: +6dB to -60dB & Mute Analog Inputs Two Stereo Inputs (TV&VCR SCART) One Stereo Input (Changeover to Internal DAC) Analog Outputs Two Stereo Outputs (TV, VCR SCART) One Mono Output (Modulator) Pop Noise Free Circuit for Power On/Off Video Section Integrated LPF SD: -40dB@27MHz HD: -40dB@74.25MHz or 54MHz or 27MHz selectable 75ohm Driver 6dB Gain for Outputs Adjustable Gain Four CVBS/Y Inputs (ENCx2, TV, VCR), Three CVBS/Y Outputs (RF, TV, VCR) Three R/C Inputs (ENCx2, VCR), Two R/C outputs (TV, VCR) Three G and B Inputs (ENC, VCR, HD), Two G and B Outputs (TV, HD) Bi-Directional Control for VCR-Red/Chroma YPbPr Option (to 6MHz) VCR Input Monitor Loop-Through Mode for Standby Auto-Startup Mode for Power Saving SCART Pin#16(Fast Blanking), Pin#8(Slow Blanking) Control S1/S2 DC Control
MS0507-E-00 -1-
2006/05
ASAHI KASEI
[AK4706]
AK4702/05 Software Compatible Power Supply 5V+/-5% and 12V+/-5% Low Power Dissipation / Low Power Standby Mode Package Small 64pin LQFP
VD1 VD2 VP VSS1 VSS2 MCLK BICK LRCK SDTI Volume #0 TV1/0 VCRINL VCRINR Volume #1 MONO TVOUTL -6dB/0dB/ +2.44/+4dB +6 to -60dB (2dB/step) VOL MONOOUT
DAC
TVOUTR
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) SCK SDA PDN Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="0")
VD1 VD2 VP VSS1 VSS2 (NC) DACL DACR (NC) Volume #2 TV1/0 VCRINL VCRINR Volume #1 MONO TVOUTR TVOUTL 0dB/+6dB +6 to -60dB (2dB/step) VOL MONOOUT
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) SCK SDA PDN Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="1")
MS0507-E-00 -2-
2006/05
ASAHI KASEI
[AK4706]
( Typical connection )
VVD1 VVD2 VVD3 VVD4 VVSS1 VVSS2 VVSS3 VVSS4 6dB RFV
( Typical connection ) RF Mod
(ENC CVBS/Y) (ENC Y) (VCR CVBS/Y) (TV CVBS)
ENCV ENCY VCRVIN TVVIN 0, 1, 2, 3dB 6dB TVVOUT
(ENC R/C/Pr) (ENC C) (VCR R/C/Pr)
ENCRC ENCC VCRRC 6dB TVRC TV SCART
(ENC G/CVBS) (VCR G)
ENCG VCRG 6dB TVG
(ENC B/Pb) (VCR B/Pb)
ENCB VCRB
6dB
TVB
mon
6dB
VCRVOUT VCR SCART
6dB VCRC
6dB (ENC R/Pr) ENCPR 6dB (ENC G/Y) ENCY2 6dB (ENC B/Pb) ENCPB
HDPR
HDY
YPbPr/RGB
HDPB
Video Block
MS0507-E-00 -3-
2006/05
ASAHI KASEI
[AK4706]
( Typical connection ) (VCR FB) VCRFB 0/4V 0/2.2/5V driver TVFB
( Typical connection )
TV SCART
0/6/12V 0/2.2/5V TVSB
VCRSB 0/ 6/ 12V
VCR SCART
Monitor
INT
Video Blanking Block
MS0507-E-00 -4-
2006/05
ASAHI KASEI
[AK4706]
Ordering Guide
AK4706VQ -10 +70C 64pin LQFP (0.5mm pitch)
Pin Layout
VVSS3 VVSS4 MCLK LRCK VVD4 VSS2 49 48 47 46 45 44 43 BICK
SDTI
PDN
SDA
SCL
VD2 51
55
62
61
59
58
52
63
60
64
57
56
HDY HDPR HDPB VVD3 RFV VCRVOUT TVFB VCRC VVSS2 TVVOUT VVD2 TVRC TVG TVB VVSS1 REFI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 18 21 17 19 20 22 23 24 32 Top View
54
53
50
VD1
NC
NC
NC
VSS1 PVCOM DVCOM VP MONOOUT TVOUTL TVOUTR VCROUTL VCROUTR TVINL TVINR VCRINL VCRINR TVSB VCRSB INT
AK4706VQ
42 41 40 39 38 37 36 35 34 33
VCRVIN
ENCRC
ENCPR
ENCPB
TVVIN
VCRRC
VCRFB
ENCY2
ENCG
VCRG
ENCC
ENCB
ENCV
ENCY
Main difference between AK4705 and AK4706
Items HD Video Driver, Filter S1/S2 Chroma DC Detector/Generator Package AK4705 48LQFP AK4706 X X 64LQFP -: NOT available. X: Available
MS0507-E-00 -5-
VCRB
VVD1
2006/05
ASAHI KASEI
[AK4706]
PIN/FUNCTION
No. 1 2 3 4 Pin Name HDY HDPR HDPB VVD3 I/O O O O Function Green/Y Output Pin Red/Pr Output Pin Blue/Pb Output Pin Video Power Supply Pin #3. 5V. Normally connected to VVSS3 with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Composite Output Pin for RF modulator Composite/Luminance Output Pin for VCR Fast Blanking Output Pin for TV Chrominance Output Pin for VCR Video Ground Pin #2. 0V. Composite/Luminance Output Pin for TV Video Power Supply Pin #2. 5V. Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Red/Chrominance/Pr Output Pin for TV Green/Y Output Pin for TV Blue/Pb Output Pin for TV Video Ground Pin #1. 0V. Video Current Reference Setup Pin Normally connected to VVD1 through a 10k1% resistor externally. Video Power Supply Pin #1. 5V. Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Green/Y Input Pin for Encoder Red/Chrominance/Pr Input Pin for Encoder Blue/Pb Input Pin for Encoder Blue/Pb Input Pin for Encoder Green/Y Input Pin for Encoder Red/Chrominance/Pr Input Pin for Encoder Chrominance Input Pin for Encoder Composite/Luminance Input1 Pin for Encoder Composite/Luminance Input2 Pin for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance/Pr Input Pin for VCR Green/Y Input Pin for VCR Blue/Pb Input Pin for VCR Interrupt Pin for Video Blanking Normally connected to VD(5V) through 10k resistor externally. Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin Rch VCR Audio Output Pin Lch VCR Audio Output Pin Rch TV Audio Output Pin Lch TV Audio Output Pin
5 6 7 8 9 10 11
RFV VCRVOUT TVFB VCRC VVSS2 TVVOUT VVD2
O O O O O -
12 13 14 15 16 17
TVRC TVG TVB VVSS1 REFI VVD1
O O O O -
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
ENCY2 ENCPR ENCPB ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT VCRSB TVSB VCRINR VCRINL TVINR TVINL VCROUTR VCROUTL TVOUTR TVOUTL
I I I I I I I I I I I I I I I O I/O O I I I I O O O O
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ASAHI KASEI
[AK4706]
PIN/FUNCTION (Continued)
44 45 MONOOUT VP O MONO Analog Output Pin Power Supply Pin. 12V. Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. DAC Common Voltage Pin Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Audio Common Voltage Pin Normally connected to VSS1 with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. The caps affect the settling time of audio bias level. Ground Pin. 0V. Ground Pin. 0V. Power Supply Pin. 5V. Normally connected to VSS2 with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Power Supply Pin. 5V. Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Master Clock Input Pin at DAPD= "0". No Connect pin at DAPD="1". This pin should be open. Audio Serial Data Clock Pin at DAPD= "0". Rch Analog Audio Input Pin at DAPD= "1". Audio Serial Data Input Pin at DAPD= "0". No Connect pin at DAPD= "1". This pin should be open. L/R Clock Pin at DAPD= "0". Lch Analog Audio Input Pin at DAPD= "1". Control Data Clock Pin Control Data Pin Power-Down Mode Pin When at "L", the AK4706 is in the power-down mode and is held in reset. The AK4706 should always be reset upon power-up. Video Ground Pin #4. 0V. No Connect pin. This pin should be connected to VSS1. Video Power Supply Pin #4. 5V. Normally connected to VVSS3 with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. No Connect pin. This pin should be connected to VSS1. Video Ground Pin #3. 0V. No Connect pin. This pin should be connected to VSS1.
46
DVCOM
O
47
PVCOM
O
48 49 50
VSS1 VSS2 VD1
-
51
VD2
-
52 53 54 55 56 57 58 59 60 61
MCLK (NC) BICK DACR SDTI (NC) LRCK DACL SCL SDA PDN VVSS4 NC VVD4
I I I I I I I I/O I -
62 63 64
NC VVSS3 NC
-
MS0507-E-00 -7-
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ASAHI KASEI
[AK4706]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Pin Name HDY, HDPR, HDPB, VCRC, TVVOUT, TVRC, TVG, TVB, ENCY2, ENCPR, ENCPB, ENCB, ENCG, ENCRC, ENCC, ENCV, ENCY, TVVIN, VCRVIN, VCRRC, VCRG, VCRB, VCRINR, VCRINL, TVINR, TVINL, VCROUTR, VCROUTL, TVOUTR, TVOUTL, MONOOUT, DACR, DACL, RFV, VCRVOUT VCRSB (O), TVFB, TVSB VCRFB, VCRSB (I), MCLK, BICK, SDTI, LRCK, SCL, SDA, INT Setting These pins should be open.
Analog
Digital
These pins should be open. These pins should be connected to VSS2.
MS0507-E-00 -8-
2006/05
ASAHI KASEI
[AK4706]
Internal Equivalent Circuits
Pin No. 52 53 54 55 56 58 Pin Name MCLK BICK SDTI LRCK SCL PDN Type Digital IN (DAPD="0") Analog IN (DAPD="1") Equivalent Circuit VD2 (60k) Description
200 VSS2
The 60k is attached only for BICK pin and LRCK pin.
VD2 200
57
SDA
Digital I/O
I2C Bus voltage must not exceed VD2.
VSS2
VVD1
33
INT
Digital OUT
Normally connected to VVD1(5V) through 10k resistor externally.
VSS1
5 6 7 8 10 12 13 14
RFV VCROUT TVFB VCRC TVVOUT TVRC TVG TVB
VVD1
VVD2
Video OUT
VVSS1 VVD4
VVSS2 VVD3
1 2 3
HDY HDPR HDPB
Video OUT
VVSS4
VVD1
VVSS3
200
16 REFI REFI IN
Normally connected to VVD1 through a 10k 1% resistor.
VVSS1
MS0507-E-00 -9-
2006/05
ASAHI KASEI
[AK4706]
Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Name ENCY2 ENCPR ENCPB ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
Type
Equivalent Circuit
Description
VVD1 200
Video IN
VVSS1
VP 200
Video SB
VP
34 35
VCRSB TVSB
(120k) VSS1 VSS1 VSS1
The 120k is not attached for TVSB pin and SDC bit = "H".
VP
36 37 38 39 VCRINR VCRINL TVINR TVINL
150k
Audio IN
VSS1 VP
40 41 42 43 44 VCROUTR VCROUTL TVOUTR TVOUTL MONOOUT
VP 100
Audio OUT
VSS1
VD1 VD1
VSS1
VD1 100
46 47
DVCOM PVCOM
VCOM OUT
VSS1 VSS1
VSS1
MS0507-E-00 - 10 -
2006/05
ASAHI KASEI
[AK4706]
ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VVSS1=VVSS2=VVSS3=VVSS4=0V;Note 1) Parameter Symbol min max Units Power Supply VD1 -0.3 6.0 V VD2 -0.3 6.0 V VVD1 -0.3 6.0 V VVD2 -0.3 6.0 V VVD3 -0.3 6.0 V VVD4 -0.3 6.0 V VP -0.3 14 V |VSS1-VVSS4| (Note 2) 0.3 V |VSS1-VVSS3| (Note 2) 0.3 V |VSS1-VVSS2| (Note 2) 0.3 V |VSS1-VVSS1| (Note 2) 0.3 V |VSS1-VSS2| (Note 2) 0.3 V Input Current (any pins except for supplies) IIN mA 10 Input Voltage (Note 3) VIND -0.3 VD2+0.3 V Video Input Voltage (Note 4.) VINV -0.3 VVD1+0.3 V Audio Input Voltage (except DACL/R pins) VINA -0.3 VP+0.3 V Audio Input Voltage (DACL/R pins) VINA -0.3 VD2+0.3 V Ambient Operating Temperature Ta -10 70 C Storage Temperature Tstg -65 150 C Note 1.All voltages with respect to ground. Note 2.VSS1, VSS2, VVSS1, VVSS2, VVSS3 and VVSS4 must be connected to the same analog ground plane. Note 3.MCLK, BICK, SDTI, LRCK, SCL, PDN pins Note 4.ENCY2, ENCPR, ENCPB, ENCB, ENCG, ENCRC, ENCC, ENCV, ENCY, TVVIN, VCRVIN, VCRFB, VCRRC, VCRG, VCRB pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VVSS1=VVSS2=VVSS3=VVSS4=0V; Note 1) Parameter Symbol min typ Power Supply (Note 5) VD1 4.75 5.0 VD2 4.75 5.0 VVD1 4.75 5.0 VVD2 4.75 5.0 VVD3 4.75 5.0 VVD4 4.75 5.0 VP 11.4 12 Note 5. Analog output voltage scales with the voltage of VD1. AOUT (typ@0dB) = 2Vrms x VD1/5. The VVD1 and VVD2 must be the same voltage.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
max 5.25 VD1 5.25 VVD1 VVD1 VVD1 12.6
Units V V V V V V V
MS0507-E-00 - 11 -
2006/05
ASAHI KASEI
[AK4706]
ELECTRICAL CHARACTERISTICS (Ta = 25C; VP=12V, VD1=VD2=5V; VVD1=VVD2=VVD3=VVD4=5V; fs = 48kHz; BICK = 64fs) Power Supplies Parameter min typ max Power Supply Current Normal Operation (PDN pin = "H"; Note 6) VD1+VD2 17 VVD1+VVD2+ VVD3+VVD4 90 VD1+VD2+ VVD1+VVD2+ VVD3+VVD4 150 VP 6 12 Power-Down Mode (PDN pin = "L"; Note 7) VD1+VD2 10 100 VVD1+VVD2+ VVD3+VVD4 10 100 VP 10 100 Note 6. STBY bit = "L", all video outputs are active. No signal, no load for A/V switches. fs=48kHz "0"data input for DAC. Note 7. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD2 or VSS2.
Units
mA mA mA mA A A A
DIGITAL CHARACTERISTICS (Ta = 25C; VD1=VD2= 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA, INT pin: Iout= 1mA) Input Leakage Current Iin -
typ -
max 0.8 0.4 100
Units V V V A
MS0507-E-00 - 12 -
2006/05
ASAHI KASEI
[AK4706]
ANALOG CHARACTERISTICS (AUDIO) (Ta = 25C; VP=12V, VD1=VD2=5V; VVD1=VVD2=VVD3=VVD4=5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz 20kHz; RL 4.5k; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2 Vrms Input Resistance 100 150 k Analog Input: (DACL/DACR pin) Analog Input Characteristics Input Voltage 1 Vrms Input Resistance 40 60 k Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note 8) Analog Output Characteristics Volume#0 Gain (DAPD bit ="0") (DVOL1-0 = "00") 0 dB (DVOL1-0 = "01") -6 dB (DVOL1-0 = "10") +2.44 dB (DVOL1-0 = "11". Note 9) +4 dB Volume#2 Gain (DAPD bit ="1") (DVOL1-0 = "00") 5.3 6.0 6.7 dB (DVOL1-0 = "01") -0.7 0 0.7 dB Volume#1 Step Width (+6dB to -12dB) 1.6 2 2.4 dB (-12dB to -40dB) 0.5 2 3.5 dB (-40dB to -60dB) 0.1 2 3.9 dB -86 -80 dB THD+N (at 2Vrms output. Note 10) -60 dB (at 3Vrms output. Note 10, Note 11) Dynamic Range (-60dB Output, A-weighted. Note 10) 92 96 dB S/N (A-weighted. Note 10) 92 96 dB Interchannel Isolation (Note 10, Note 12) 80 90 dB Interchannel Gain Mismatch (Note 10, Note 12) 0.3 dB Gain Drift 200 ppm/C Load Resistance (AC-Lord; Note 13) TVOUTL/R, VCROUTL/R, MONOOUT 4.5 k Load Capacitance TVOUTL/R, VCROUTL/R, MONOOUT 20 pF Output Voltage (Note 13, Note 14) 1.85 2 2.15 Vrms Power Supply Rejection (PSR. Note 15) 50 dB Note 8. Measured by Audio Precision System Two Cascade. Note 9. Output clips over -2.5dBFS digital input. Note 10. DAC to TVOUT Note 11. Except VCROUTL/VCROUTL pins. Note 12. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS. Note 13. THD+N: -80dB(min. at 2Vrns), -60dB(typ. at 3Vrms). Note 14. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD1, Stereo output (typ@0dBFS) = 2Vrms x VD1/5 when volume#0=volume#1=0dB. The output must not exceed 3Vrms. Note 15. The PSR is applied to VD1 with 1kHz, 100mV.
MS0507-E-00 - 13 -
2006/05
ASAHI KASEI
[AK4706]
FILTER CHARACTERISTICS (Ta = 25C; VP=11.412.6V, VD1=VD2=4.755.25V, VVD1=VVD2=VVD3=VVD4=4.755.25V; fs = 48kHz; DEM0 = "1", DEM1 = "0") Parameter Symbol min typ max Units Digital filter PB 0 21.77 kHz Passband 0.05dB (Note 16) 24.0 kHz -6.0Db Stopband (Note 16) SB 26.23 kHz Passband Ripple PR dB 0.01 Stopband Attenuation SA 64 dB Group Delay (Note 17) GD 24 1/fs Digital Filter + LPF FR dB Frequency Response 0 20.0kHz 0.5
Note 16. The passband and stopband frequencies scale with fs. e.g.) PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note 17. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18/24bit data of both channels to input register to the output of analog signal.
MS0507-E-00 - 14 -
2006/05
ASAHI KASEI
[AK4706]
ANALOG CHARACTERISTICS (SD VIDEO) (Ta = 25C; VP=12V, VD1=VD2=5V; VVD1=VVD2=VVD3=VVD4=5V; VVOL1/0= "00", unless otherwise specified.) Parameter Conditions min typ max Units Sync Tip Clamp Voltage at output pin. 0.7 V Chrominance Bias Voltage at output pin. 2.2 V R/G/B Clamp Voltage at output pin. 0.7 V Pb/Pr Clamp Voltage at output pin. 2.2 V Gain Input=0.3Vp-p, 100kHz 5.5 6 6.5 dB RGB Gain Input=0.3Vp-p, VVOL1/0= "00" 5.5 6 6.5 dB 100kHz VVOL1/0= "01" 6.7 7.2 7.7 dB VVOL1/0= "10" 7.7 8.2 8.7 dB VVOL1/0= "11" 8.6 9.1 9.6 dB Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz -0.5 0.5 dB Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz. -1.0 0.5 dB at 10MHz. -3 dB at 27MHz. -40 -25 dB Group Delay Distortion At 4.43MHz with respect to 1MHz. 15 ns Input Impedance Chrominance input (internally biased) 40 60 k Input Signal f=100kHz, distortion < 1.0%, gain=6dB 1.5 Vpp Load Resistance (Note 18) 150 Load Capacitance C1 (Note 18) 400 pF C2 (Note 18) 15 pF Dynamic Output Signal f=100kHz, distortion < 1.0% 3 Vpp Y/C Crosstalk f=4.43MHz, 1Vp-p input. Among TVVOUT, -50 dB TVRC, VCRVOUT and VCRC outputs. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. 74 dB BW= 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. +0.3 % chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. +0.6 Degree chrominance &burst are 280mVpp, 4.43MHz. Note 18. Refer the Figure 1.
R1 75 Video Signal Output C2 max: 15pF C1 max: 400pF R2 75
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
MS0507-E-00 - 15 -
2006/05
ASAHI KASEI
[AK4706]
ANALOG CHARACTERISTICS (HD VIDEO) (Ta = 25C; VP=12V, VD1=VD2=5V; VVD1=VVD2=VVD3=VVD4=5V; VVOL1/0= "00", unless otherwise specified.) Parameter Conditions min typ max Units Sync Tip Clamp Voltage at output pin. 0.7 V R/G/B Clamp Voltage at output pin. 0.7 V Pb/Pr Clamp Voltage at output pin. 2.2 V Gain Input=0.3Vp-p, 100kHz 5.5 6 6.5 dB Frequency response Input=0.3Vp-p, FL1/0,FLPB1/0,FLPR1/0= "10" C1=C2=0pF 100kHz to 20MHz, -1.0 1.0 dB (Note 18) at 30MHz. -2.5 dB at 74.25MHz. -40 -25 dB FL1/0,FLPB1/0,FLPR1/0= "01" 100kHz to 15MHz, -1.0 1.0 dB at 54MHz. -40 -25 dB FL1/0,FLPB1/0,FLPR1/0= "00" 100kHz to 6MHz, -1.0 0.5 dB at 27MHz. -40 -25 dB Input Signal f=100kHz, distortion < 1.0%, gain=6dB 1.5 Vpp
Load Resistance Load Capacitance Dynamic Output Signal Differential Gain Differential Phase C1 C2 f=100kHz, distortion < 1.0% (Figure 1) (Figure 1) (Figure 1) 150 400 10 3 pF pF Vpp % Degree
-
+0.3 +0.6
0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. FL1/0,FLPB1/0,FLPR1/0= "00" 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. FL1/0,FLPB1/0,FLPR1/0= "00"
MS0507-E-00 - 16 -
2006/05
ASAHI KASEI
[AK4706]
SWITCHING CHARACTERISTICS (Ta = 25C; VP=11.4 12.6V, VD1=VD2=4.75 5.25V, VVD1=VVD2=VVD3=VVD4=4.75 5.25V; CL = 20pF) Parameter Symbol Min typ max Units fCLK 8.192 12.8 MHz Master Clock Frequency 256fs: dCLK 40 60 % Duty Cycle fCLK 12.288 19.2 MHz 384fs: dCLK 40 60 % Duty Cycle fs 32 50 kHz LRCK Frequency Duty 45 55 Duty Cycle % Audio Interface Timing tBCK 312.5 ns BICK Period tBCKL 100 ns BICK Pulse Width Low tBCKH 100 ns Pulse Width High tBLR 50 ns BICK "" to LRCK Edge (Note 19) tLRB 50 ns LRCK Edge to BICK "" (Note 19) tSDH 50 ns SDTI Hold Time tSDS 50 ns SDTI Setup Time Control Interface Timing (I2C Bus): 400 kHz SCL Clock Frequency fSCL 1.3 s Bus Free Time Between Transmissions tBUF 0.6 s Start Condition Hold Time tHD:STA (prior to first clock pulse) s 1.3 Clock Low Time tLOW s 0.6 Clock High Time tHIGH s 0.6 Setup Time for Repeated Start Condition tSU:STA s 0 SDA Hold Time from SCL Falling (Note 20) tHD:DAT s 0.1 SDA Setup Time from SCL Rising tSU:DAT 0.3 s Rise Time of Both SDA and SCL Lines tR 0.3 s Fall Time of Both SDA and SCL Lines tF 0.6 s Setup Time for Stop Condition tSU:STO 0 50 ns tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing tPD 150 ns PDN Pulse Width (Note 21) Note 19. BICK rising edge must not occur at the same time as LRCK edge. Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 21. The AK4706 should be reset by PDN pin = "L" upon power up. Note 22. I2C is a registered trademark of Philips Semiconductors.
MS0507-E-00 - 17 -
2006/05
ASAHI KASEI
[AK4706]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL tBCK VIH VIL tBCKH tBCKL
LRCK
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Serial Interface Timing
MS0507-E-00 - 18 -
2006/05
ASAHI KASEI
[AK4706]
VIH SDA VIL tBUF SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start
I2C Bus mode Timing
tLOW
tR
tHIGH
tF
tSP VIH
tSU:STO Stop
tPD
PDN
VIL
Power-down Timing
MS0507-E-00 - 19 -
2006/05
ASAHI KASEI
[AK4706]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4706 should be reset once by bringing PDN pin = "L" upon power-up. The AK4706 has several operation modes. The PDN pin, AUTO bit, DAPD bit, MUTE bit and STBY bit control operation modes as shown in Table 1 and Table 2. Mode 0 1 2 3 4 5 6 7 PDN pin "L" "H" "H" "H" "H" "H" "H" "H" AUTO bit * 1 0 0 0 0 0 0 STBY bit * * 1 1 0 0 0 0 MUTE bit * * 1 0 1 1 0 0 DAPD bit * * * * 1 0 1 0 Mode Full Power-down Auto Startup mode (default) Standby & mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down & Analog input) Normal operation (DAC operation) *: Don't Care
Table 1. Operation Mode Settings Audio MCLK, BICK, LRCK Not needed Video Output Audio Bias Level Power down Video Signal Hi-Z TVFB, TVSB Hi-Z VCRSB Pull-down (2)
Mode 0 1 Full Power-down Auto Startup mode No video input Auto Startup mode Video input (3) Standby & mute Standby Mute1 Mute2 Normal operation (DAC power down & Analog input) Normal operation (DAC operation)
Register Control NOT available Available
DAC Power down
Active Power down Active Power down Active (1)
2 3 4 5 6 7
Active (4) Hi-Z/ Active
Active
Active
Active Power down Active
Needed Not needed Needed
Notes: (1) TVOUTL/R are muted by VMUTE bit in the default state. (2) Internally pulled down by 120kohm(typ) resistor. (3) Video input to TVVIN or VCRVIN. (4) VCRC outputs 0V for termination. HD Video output does not work. (Hi-Z default) Table 2. Status of each operation modes
MS0507-E-00 - 20 -
2006/05
ASAHI KASEI
[AK4706]
System Reset and Full Power-down Mode
The AK4706 should be reset once by bringing PDN pin = "L" upon power-up. PDN pin: Power down pin "H": Normal operation "L": Device power down.
Auto Startup Mode
When the PDN pin is set to "H", the AK4706 is in the auto startup mode. In this mode, all blocks except for the video detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN pin, the AK4706 goes to the stand-by mode (Both Fast Blanking and Slow Blanking are also fixed to VCR-TV Loop-through) automatically and sends "H" pulse via INT pin. To exit the auto startup mode, set the AUTO bit to "0". The HD video outputs in the auto startup mode are disable at power-up. In this mode, HD video outputs are controlled as shown in Table 3. AUTO bit (00H D3): Auto startup bit (SD Video output) "1": Auto startup enable (default). "0": Auto startup disable (Manual startup). HDAPW bit (0AH D5): Auto startup bit (HD Video output) "1": Auto startup enable. "0": Auto startup disable (Manual startup: default). AUTO bit 0 0 1 1 HDAPW bit 0 1 0 1 HD Video output Set by HDSW1/0, HDCP1/0 bit Hi-Z Hi-Z Set by HDSW1/0, HDCP1/0 bit after a video signal is detected. Table 3. HD Video output status
The Figure 2 shows an example of the system timing at auto startup mode.
Auto startup enable
PDN pin AUTO bit HDAPW bit Clock, Data in TVVIN VCRVIN TVVOUT, VCRVOUT HD Video OUTPUT Audio out (DC)
don't care
Low Power Mode
Low Power Mode
Low Power Mode
"1"(defaoult) "0" (default) "1"
don't care
No Signal
Signal in
No Signal
Signal in
No Signal
don't care
don't care
No Signal
Signal in
No Signal
don't care
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through)
Hi-Z
Hi-Z
Active Active (loop-through)
Hi-Z
Active Active (loop-through)
Hi-Z
(GND)
Figure 2.Auto startup mode sequence MS0507-E-00 - 21 2006/05
ASAHI KASEI
[AK4706]
DAC Power-down Mode
The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit ="1", the zero-cross detection and offset calibration does not work. DAPD bit (00H D2): DAC power-down bit. "1": DAC power-down. Analog-input mode. #52 pin: MCLK Unused pin. This pin should be open. #53 pin: BICK DACR. Rch analog input. #54 pin: SDTI Unused pin. This pin should be open. #55 pin: LRCK DACL. Lch analog input. "0": DAC operation. (default)
Standby Mode
When the AUTO bit = MUTE bit = "0" and the STBY bit = "1", the AK4706 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values themselves are NOT changed by STBY bit = "1". STBY bit (00H D0): Standby bit. "1": Standby mode. (default) "0": Normal operation.
Mute Mode (Bias-off Mode. 00H: D1)
When the MUTE bit = "1", the bias voltage on the audio output goes to GND level. Bringing MUTE bit to "0" changes this bias voltage smoothly from GND to VP/2 by 2sec(typ.). This removes the huge click noise related the sudden change of bias voltage at power-on. The change of MUTE bit from "1" to "0" also makes smooth transient from VP/2 to GND by 2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off. MUTE bit: Bias-off bit. "1": Set the audio bias to GND. (default) "0": Normal operation
Normal Operation Mode
To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bit and STBY bit to "0". The DAC is in power-down mode until MCLK and LRCK are input. The AK4706 is in power-down mode until MCLK and LRCK are input. The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin.
MS0507-E-00 - 22 -
2006/05
ASAHI KASEI
[AK4706]
Typical Operation Sequence
The Figure 3 shows an example of the system timing.
PDN pin AUTO bit MUTE bit STBY bit Clock in Data in
D/A Out (internal)
"Stand-by" "Mute" "Stand-by"
"1" (default) "1" (default) "1" (default)
don't care (2) don't care "0" GD
"0" "0" "1" "0"
normal operation Audio data "0" GD (1)
"0" "1"
"1"
don't care (2) don't care
(1)
TV-Source select
fixed to VCR in(Loop-through)
VCR in (default)
DAC
VCR in
TV out
VCR in
VCR in
(3)
Figure 3. Typical operating sequence (except auto setup mode) Notes: (1) The analog output corresponding to the digital input has a group delay, GD. (2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode. (3) Mute the analog outputs externally if click noise(3) adversely affects the system. (4) The HDSW1/0, HDCP1/0 bits set HD video outputs.
HD Video Output id
Hi-z
normal operation(4)
Hi-z
MS0507-E-00 - 23 -
2006/05
ASAHI KASEI
[AK4706]
2. Audio Block
System Clock
The external clocks required to operate the DAC section of AK4706 are MCLK, LRCK and BICK. The master clock (MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 4 illustrates corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC section of AK4706 is in the normal operating mode (STBY bit = "0" and DAPD bit = "0"). If these clocks are not provided, the AK4706 may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4706 should be reset by STBY bit = "0" after threse clocks are provided. If the external clocks are not present, place the AK4706 in power-down mode (STBY bit = "1"). After exiting reset at power-up etc., the AK4706 remains in power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz MCLK 256fs 384fs 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz Table 4. System clock example BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Audio Serial Interface Format (00H: D5-D4)
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial mode as shown in Table 5. In all modes, the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTI Format 16bit LSB Justified 18bit LSB Justified 24bit MSB Justified BICK 32fs 36fs 48fs 48fs or 2 24bit I S Compatible 32fs Table 5. Audio Data Formats Figure Figure 4 Figure 4 Figure 5 Figure 6 Default
MS0507-E-00 - 24 -
2006/05
ASAHI KASEI
[AK4706]
LRCK BICK SDTI Mode 0 SDTI Mode 1
Don't care 15:MSB, 0:LSB Don't care 17:MSB, 0:LSB 17 16
15 14
0
Don't care
15 14
0
15
14
0
Don't care
17
16
15
14
0
Lch Data
Figure 4. Mode 0,1 Timing
Rch Data
LRCK BICK SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 0 Don't care
23 22
1
17
16
Lch Data
Figure 5. Mode 2 Timing
Rch Data
LRCK BICK SDTI
1 0 Don't care 0 17
23 22 23:MSB, 0:LSB
23 22
1
Don't care
Lch Data
Figure 6. Mode 3 Timing
Rch Data
MS0507-E-00 - 25 -
2006/05
ASAHI KASEI
[AK4706]
De-emphasis filter (00H: D7-D6)
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is controlled by the DEM0 and DEM1 bits. DEM1 DEM0 Mode default
0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 6. De-emphasis filter control
Switch Control
The AK4706 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in Table 7, Table 8 and Table 9 (refer to the block diagram). (01H: D1-D0) TV1 TV0 Source of TVOUTL/R 0 0 DAC 0 1 VCRIN (default) 1 0 Mute 1 1 (Reserved) Table 7. TVOUT Switch Configuration (01H: D2-D0) VOL TV1 TV0 Source of MONOOUT 0 0 0 DAC (L+R)/2 Bypass the 0 0 1 DAC (L+R)/2 volume #1 0 1 0 DAC (L+R)/2 0 1 1 (Reserved) Through the 1 0 0 DAC (L+R)/2 volume #1 1 0 1 VCRIN (L+R)/2 1 1 0 Mute 1 1 1 (Reserved) Table 8. MONOOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 Source of VCROUTL/R 0 0 DAC 0 1 TVIN (default) 1 0 Mute 1 1 Output of volume #1 Table 9. VCROUT Switch Configuration
MS0507-E-00 - 26 -
2006/05
ASAHI KASEI
[AK4706]
Volume Control #0, #2 (4-Level Volume)
The AK4706 has a 4-level volume control (Volume #0, #2) as shown in Table 10 and Table 11. The volume reflects the change of register value immediately. (03H: D4-D3) DVOL1 0 0 1 1
DVOL0 0 1 0 1
Output Level (Typ) 2Vrms (with 0dBFS input & volume #1=0dB.) 1Vrms (with 0dBFS input & volume #1=0dB.) 2.65Vrms (with 0dBFS input & volume #1=0dB.) 2Vrms (with -10dBFS input & volume #1=+6dB. +4dB Clips over -2.5dBFS digital input.) Table 10. Volume #0 (at DAPD bit ="0". DAC mode)
Volume #0 Gain 0dB -6dB +2.44dB
(03H: D4-D3) DVOL1 0 0 1 1
DVOL0 Volume #2 Gain Output Level (Typ) 0 +6dB 2Vrms (with 1Vrms input & volume #1=0dB.) 1 0dB 1Vrms (with 1Vrms input & volume #1=0dB.) 0 (reserved) 1 (reserved) Table 11. Volume #2 (at DAPD bit ="1". analog input mode.)
MS0507-E-00 - 27 -
2006/05
ASAHI KASEI
[AK4706]
Volume Control #1 (Main Volume)
The AK4706 has main volume control (Volume #1) as shown in Table 12. (02H: D5-D0) L5 L4 L3 L2 L1 L0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 ... ... ... ... ... ... 0 0 0 0 0 1 0 0 0 0 0 0 Note: The output must not exceed 3Vrms. Table 12. Volume #1
Gain +6dB +4dB +2dB 0dB (default) ... -60dB Mute
When the MOD bit = "1"(default), changing levels don't have pop noise. MDT1-0 bits select the transition time (see Table 13). When the new gain value 1EH(-2dB) is written to gain resistor while the actual (stable) gain is 1FH(0dB), the gain changes to 1EH(-2dB) within the transition time selected by MDT1-0 bits. The AK4706 compares the actual gain to the value of gain register after finishing the transition time, and re-changes the actual gain to new resister value within the transition time if the register value is different from the actual gain when compared. When the MOD bit = "0" then there is no transition time and the gain changes immediately. This change may cause a click noise.
WR [Gain=1EH] WR [Gain=1DH] WR [Gain=1CH]
Gain Register
1FH
1EH compare
1DH
1CH compare compare 1CH
Actual Gain
1FH (to 1EH)
1EH
(to 1DH)
(to 1CH)
1DH Transition Time (256/fs to 2048/fs. pop free.)
Figure 7. Volume Change Operation (MOD bit = "1") MDT1 0 0 1 1 MDT0 Transition Time 0 256/fs 1 512/fs 0 1024/fs 1 2048/fs (default) Table 13. Volume Transition Time
MS0507-E-00 - 28 -
2006/05
ASAHI KASEI
[AK4706]
3. Video Block
Video Switch Control
The AK4706 has switches for TV, VCR and RF modulator. Each switches can be controlled via registers independently. When AUTO bit = "1" or STBY bit = "1", these switch setting are ignored and set to fixed configuration (loop-through mode). Please refer the auto setup mode and standby mode. (04H: D2-D0) Mode Shutdown Encoder CVBS+RGB or Encoder YPbPr Encoder Y/C 1 Encoder Y/C 2 VCR (default) TV CVBS (reserved) (reserved) VTV2-0 bit 000 001 010 011 100 101 110 111 Source of TVVOUT pin (Hi-Z) ENCV pin (Encoder CVBS or Y) ENCV pin (Encoder Y) ENCY pin (Encoder Y) VCRVIN pin (VCR CVBS or Y) TVVIN pin (TV CVBS) Source of TVRC pin (Hi-Z) ENCRC pin (Encoder Red,C or Pb) ENCRC pin (Encoder C) ENCC pin (Encoder C) VCRRC pin (VCR Red,C or Pb) (Hi-Z) Source of TVG pin (Hi-Z) ENCG pin (Encoder Green or Y) (Hi-Z) (Hi-Z) VCRG pin (VCR Green or Y) (Hi-Z) Source of TVB pin (Hi-Z) ENCB pin (Encoder Blue or Pr) (Hi-Z) (Hi-Z) VCRB pin (VCR Blue or Pr) (Hi-Z)
(Refer Note 23, Note 24)
Table 14. TV video output (04H: D5-D3) Mode Shutdown Encoder CVBS or Y/C 1 Encoder CVBS or Y/C 2 TV CVBS (default) VCR (reserved) (reserved) (reserved) VVCR2-0 bit 000 001 010 011 100 101 110 111 Source of VCRVOUT pin (Hi-Z) ENCV pin (Encoder CVBS or Y) ENCY pin (Encoder CVBS or Y) TVVIN pin (TV CVBS) VCRVIN pin (VCR CVBS) Source of VCRC pin (Hi-Z) ENCRC pin (Encoder C) ENCC pin (Encoder C) (Hi-Z) VCRRC pin (VCR C) (Refer Note 23)
Table 15. VCR video output
MS0507-E-00 - 29 -
2006/05
ASAHI KASEI
[AK4706]
(04H: D7-D6) Source of RFV pin ENCV pin. Encoder CVBS1 00 (Encoder CVBS) ENCG pin. Encoder CVBS2 01 (Encoder CVBS) (Note 24) VCRVIN pin. VCR (default) 10 (VCR CVBS) Shutdown 11 (Hi-Z) Table 16. RF video output Mode Note 23. When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively. Note 24. When VTV2-0 bit ="001", TVG bit ="1" and VRF1-0 bit ="01", RFV pin output is same as TVG pin output (Encoder G). VRF1-0 bit
Video Output Control (05H: D6-D0)
Each video outputs can be set to Hi-Z individually via control registers. These setting are ignored when the AUTO bit = "1". When the CIO bit = "1", the VCRC pin outputs 0V even if the VCRC bit = "0". When the CIO bit = "0", the VCRC pin follows the setting of VCRC bit. Please refer the "Red/Chroma Bi-directional Control for VCR SCART". TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB: TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control TVFB output control
0: Hi-Z (default) 1: Active.
Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The AK4706 supports the bi-directional Red/Chroma signal on the VCR SCART.
(CIO bit & VCRC bit) 75 VCRC pin
#15 pin
VCRRC pin VCR SCART 0.1u
(AK4706)
Figure 8. Red/Chroma Bi-directional Control MS0507-E-00 - 30 2006/05
ASAHI KASEI
[AK4706]
CIO 0 0 1 1
VCRC State of VCRC pin 0 Hi-Z (default) 1 Active 0 Connected to GND 1 Connected to GND Table 17 Red/Chroma Bi-directional Control
RGB Video Gain Control (06H: D1-D0)
VVOL1-0 bits set the RGB video gain. VVOL1 0 0 1 1 VVOL0 0 1 0 1 Gain Output level (Typ. @Input=0.7Vpp) +6dB 1.4Vpp (default) +7.2dB 1.6Vpp +8.2dB 1.8Vpp +9.1dB 2.0Vpp Table 18. RGB video gain control
Clamp and DC-restore circuit control (06H: D7-D2, 0AH: D3)
Each CVBS and Y input has the sync tip clamp circuit. The DC-restore circuit has two clamp voltages 0.7V(typ) and 2.2V(typ) to support both RGB and YPbPr signal. They correspond to 0.35V(typ) and 1.1V(typ) at the SCART connector when matched by 75ohm resistors. The CLAMP1, CLAMP0 and CLAMPB bits select the input circuit for ENCRC pin (Encoder Red/Chroma), ENCB pin (Encoder Blue), VCRRC pin (VCR Red/Chroma) and VCRB pin (VCR Blue) respectively. VCLP1-0 bits select the sync source of DC- restore circuit. CLAMPB 0 0 1 1 CLAMP0 0 1 0 1 VCRRC Input Circuit VCRB Input Circuit VCRG Input Circuit DC restore (0.7V) DC restore (0.7V) DC restore (0.7V) Biased DC restore (0.7V) DC restore (0.7V) DC restore (2.2V) DC restore (2.2V) Sync Tip Clamp (0.7V) (reserved) (reserved) (reserved) Table 19. DC-restore control for VCR Input ENCRC Input Circuit ENCB Input Circuit DC restore (0.7V) DC restore (0.7V) Biased DC restore (0.7V) DC restore (2.2V) DC restore (2.2V) (reserved) (reserved) Table 20. DC-restore control for Encoder Input CLAMP2 0 1 ENCG Input Circuit DC restore (0.7V) Sync tip clamp (0.7V) note for RGB for YPbPr note for RGB for Y/C for YPbPr
default
CLAMPB 0 0 1 1
CLAMP1 0 1 0 1
note for RGB for Y/C for YPbPr
default
default
Note: When the VTV2-0 bits = "001", TVG bit ="1" and VCLP2-0 bits = "011", Sync tip is selected even if the CLAMP2 bit = "0". Table 21. DC-restore control for Encoder Green/Y Input
MS0507-E-00 - 31 -
2006/05
ASAHI KASEI
[AK4706]
VCLP2-0: DC restore source control VCLP2 0 0 0 0 VCLP1 0 0 1 1 VCLP0 0 1 0 1 Sync Source of DC Restore ENCV (default) ENCY VCRVIN ENCG
1 0 0 VCRG 1 0 1 (reserved) 1 1 0 (reserved) 1 1 1 (reserved) Note: When the AUTO bit = "1", the source is fixed to VCRVIN. Table 22. DC-restore source control
HD Video Control (0AH: D7-D6, D1-D0)
FLY1/0, FLPB1/0, FLPR1/0 bits and HDSW1/0, HDCP1/0 bits set the HD video switch and filter response. HDSW1 HDSW0 HD YPbPr - RGB Control YPbPr. ENCY2 = 0.7V Clamp, 0(default) 0(default) ENCPB = 2.2V DC-restore, /1 ENCPR = 2.2V DC-restore. (ENCY2= Sync Source only for ENCPB, ENCPR) RGB. ENCY2 = 0.7V Clamp, 1 0 ENCPB = 0.7V DC-restore, ENCPR = 0.7V DC-restore. (ENCY2= Sync Source only for ENCPB, ENCPR) RGB. ENCY2 = 0.7V DC-restore, 1 1 ENCPB = 0.7V DC-restore, ENCPR = 0.7V DC-restore. Sync Source = ENCV ENCG, ENCB, * * ENCR Follow CLAMPB, 2, 1 VCRG, VCRB, * * VCRRC Follow CLAMPB, 0. VCRG follow VCRRC circuit. * * Hi-Z Table 23. HD Video Switch Control (3ch common) HDCP1 HDCP0
0
0
0
0
0
0
0
1
1
0
1(default)
1(default)
Input Output FLY1/ FLPB1/FLPR1 bit FLY0/ FLPB0/FLPR0 bit LFP response 0 0 6MHz LPF (default) 0 1 12MHz LPF 1 0 30MHz LPF 1 1 (Reserved) Table 24. HD Video Filter Control (3ch independent)
MS0507-E-00 - 32 -
2006/05
ASAHI KASEI
[AK4706]
4. Blanking Control, S1/S2 DC Control
When the SDC bit= "0", the AK4706 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART. When the SDC bit= "1", the AK4706 supports S1/S2 mode. SDC bit: SCART-S1/S2 Control 0: SCART Fast/Slow Blanking Mode 1: S1/S2 Mode
Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (0AH: D4, 07H: D1-D0) Input FB1 bit 0 0 1 1 Output TVFB pin Output Level <0.4V (default) 4V< Same as VCR FB input (4V/0V) (Reserved)
SDC bit 0 0 0 0 1 1 1 1
FB0 bit 0 1 0 1
0 0 <0.4V 0 1 1.55V to 2.4V 1 0 Same as VCR FB input (5V/2.2V/0V) 1 1 3.5V< (Note: Load resistance is min.150ohm for SDC bit ="0", min.100kohm for SDC bit ="1") Table 25. TV Fast Blanking output
SBT1-0: TV Slow Blanking output control (0AH: D4, 07H: D3-D2) Input SBT1 bit 0 0 1 1 Output SBT0 bit 0 1 0 1 TVSB pin Output Level <2V (default) 5V to 7V (Reserved) 10V<
SDC bit 0 0 0 0 1 1 1 1
0 0 <0.4V 0 1 1.55V to 2.4V 1 0 (Reserved) 1 1 3.5V< (Note: Load resistance is min.10kohm for SDC bit ="0", min.100kohm for SDC bit ="1") Table 26. TV Slow Blanking output
SBV1-0: VCR Slow Blanking output control (07H: D5-D4) SBV1 0 0 1 1 VCRSB pin Output Level <2V (default) 5V to 7V (Reserved) 10V< (Note: Load resistance is min.10kohm) Table 27. VCR Slow Blanking output SBV0 0 1 0 1
MS0507-E-00 - 33 -
2006/05
ASAHI KASEI
[AK4706]
SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6) SBIO1 0 0 1 1 SBIO0 0 1 0 1 VCRSB pin Direction TVSB pin Direction Output Output (Controlled by SBV1,0) (Controlled by SBT1,0) (Reserved) (Reserved) Input Output (Stored in SVCR1,0) (Controlled by SBT1,0) Input Output (Stored in SVCR1,0) (Same output as VCR SB) Table 28. TV/VCR Slow Blanking I/O control
(default)
MS0507-E-00 - 34 -
2006/05
ASAHI KASEI
[AK4706]
5. Monitor Options and INT function
Monitor Options (08H: D7, D5, D2-D0)
The AK4706 has several detection functions. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit reflect the input DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins. SDC bit: SCART-S1/S2 Control 0: SCART Fast/Slow Blanking Mode 1: S1/S2 Mode SVCR1-0 bit: VCR Slow blanking status monitor SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB pin is in the input mode. When the VCRSB is in the output mode, SVCR1-0 hold previous value. Input VCRSB pin input level < 2V 4.5 to 7V (Reserved) 9.5< Output SVCR1 bit 0 0 1 1
SDC bit 0 0 0 0
SVCR0 bit 0 1 0 1
1 < 0.4V 0 0 1 1.4 to 2.4V 0 1 1 (Reserved) 1 0 1 3.5V< 1 1 Note: When SDC bit ="0", VCRSB pin is connected to a Internal pull-down resistor(120k@TYP). Table 29. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". Input VCRFB pin input level <0.4V 1 V< (Reserved) (Reserved) < 0.4V 1.4 to 2.4V (Reserved) 3.5V< Output FVCR1 bit 0 0 0 0 0 0 1 1
SDC bit 0 0 0 0 1 1 1 1
FVCR0 bit 0 1 0 0 0 1 0 1
Table 30. VCR Fast Blanking monitor (Typical threshold is 0.7V)
MS0507-E-00 - 35 -
2006/05
ASAHI KASEI
[AK4706]
VCMON: VCRVIN pin video input monitor (MCOMN bit ="1"), TVVIN pin or VCRVIN pin video input monitor (MCOMN bit = "0") 0: No video signal detected. 1: Detects video signal. TVMON: TVVIN pin video input monitor (active when MCOMN bit = "1") 0: No video signal detected. 1: Detects video signal.
MCOMN (09H D7) 0 0 0 0 1 1 1 1 TVVIN signal* 0 0 1 1 0 0 1 1 VCRVIN signal* 0 1 0 1 0 1 0 1 TVMON (08H D4) 0 0 0 0 0 0 1 1 VCMON (08H D3) 0 1 1 1 0 1 0 1
*: "0" is No signal. "1" is Signal input Table 31. TV/VCR Monitor Function
MS0507-E-00 - 36 -
2006/05
ASAHI KASEI
[AK4706]
INT Function and Mask Options (09H: D7, D4-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes "L" for 2sec(typ.) when the status of 08H is changed. This pin should be connected to VD2 (typ. 5V) through 10kohm resistor. MTV bit, MVC bit, MCOMN bit, MFVCR bit and MSVCR bit control the reflection of the status change of these monitors onto the INT pin from report to prevent to masks each monitor.
AK4706
VD2 R=10k INT uP
Figure 9. INT pin MVC: VCMON Mask. Refer Table 33 MTV: TVMON Mask. Refer Table 32 MCOMN: Refer Table 31 AUTO (00H D3) 0 0 0 0 1 1 1 1 TVMON (08H D4) No Change No Change Change Change MTV (09H D4) 0 1 0 1 INT Hi-Z Hi-Z Generates "L" Pulse Hi-Z Hi-Z Hi-Z Generates "L" Pulse Generates "L" Pulse
No Change 0 No Change 1 Change 0 Change 1 Table 32. TV Monitor Mask VCMON (08H D3) No Change No Change Change Change MVC (09H D3) 0 1 0 1
AUTO (00H D3) 0 0 0 0 1 1 1 1
INT Hi-Z Hi-Z Generates "L" Pulse Hi-Z Hi-Z Hi-Z Generates "L" Pulse Generates "L" Pulse
No Change 0 No Change 1 Change 0 Change 1 Table 33. VCR Monitor Mask
MFVCR: FVCR Monitor mask. 0: Change of MFVCR is reflected to INT pin. (default) 1: Change of MFVCR is NOT reflected to INT pin. MSVCR: SVCR1-0 Monitor mask 0: Change of SVCR1-0 is reflected to INT pin. (default) 1: Change of SVCR1-0 is NOT reflected to INT pin.
MS0507-E-00 - 37 -
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ASAHI KASEI
[AK4706]
6. Control Interface
I2C-bus Control Mode
1. WRITE Operations Figure 10 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 16). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0010001". If the slave address match that of the AK4706, the AK4706 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 17). A "1" for R/W bit indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4706. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 12). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 13). The AK4706 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 16). The AK4706 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4706 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 0BH prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 18) except for the START and the STOP condition.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W= "0"
SDA
S
Slave Address A C K
Sub Address(n)
Figure 10. Data transfer sequence at the I2C-bus mode 0 0 1 0 0 0 1 R/W
Figure 11. The first byte 0 0 0 A4 A3 A2 A1 A0
Figure 12. The second byte D7 D6 D5 D4 D3 D2 D1 D0
Figure 13. Byte structure after the second byte
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ASAHI KASEI
[AK4706]
2. READ Operations Set R/W bit = "1" for READ operations. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4706 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-1. CURRENT ADDRESS READ The AK4706 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4706 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4706 discontinues transmission
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 14. CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address(R/W="0") and then the register address to read. After the register's address is acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4706 generates an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4706 discontinues transmission.
S T A R T R/W= "0" S T A R T S A C K Slave Address A C K R/W= "1" S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 15. RANDOM ADDRESS READ
MS0507-E-00 - 39 -
2006/05
ASAHI KASEI
[AK4706]
SDA
SCL S start condition P stop condition
Figure 16. START and STOP conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 17. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 18. Bit transfer on the I2C-bus
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ASAHI KASEI
[AK4706]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Register Name Control Switch Main volume Zerocross Video switch Video output enable Video volume/clamp S/F Blanking control S/F Blanking monitor Monitor mask HD switch HD filter D7
DEM1 VMUTE 0 0 VRF1 CIO CLAMPB SBIO1 0 MCOMN HDCP1 0
D6
DEM0 0 0 VMONO VRF0 TVFB VCLP1 SBIO0 0 0 HDCP0 0
D5
DIF1 VCR1 L5 1 VVCR2 VCRC VCLP0 SBV1 FVCR1
D4
DIF0 VCR0 L4 DVOL1 VVCR1 VCRV CLAMP2 SBV0 TVMON MTV
D3
AUTO MONO L3 DVOL0 VVCR0 TVB CLAMP1 SBT1 VCMON MVC VCLP2 FLPB1
D2
DAPD VOL L2 MOD VTV2 TVG CLAMP0 SBT0 FVCR0 MFVCR 0 FLPB0
D1
MUTE TV1 L1 MDT1 VTV1 TVR VVOL1 FB1 SVCR1 MSVCR HDSW1 FLY1
D0
STBY TV0 L0 MDT0 VTV0 TVV VVOL0 FB0 SVCR0 0 HDSW0 FLY0
HDAPW FLPR1
SDC FLPR0
When the PDN pin goes "L", the registers are initialized to their default values. While the PDN pin ="H", all registers can be accessed. Do not write any data to the register over 0BH.
MS0507-E-00 - 41 -
2006/05
ASAHI KASEI
[AK4706]
Register Definitions
Addr 00H Register Name Control R/W default 0 1 1 1 D7 DEM1 D6 DEM0 D5 DIF1 D4 DIF0 R/W 1 0 1 1 D3 AUTO D2 DAPD D1 MUTE D0 STBY
STBY: Standby control 0: Normal Operation 1: Standby Mode (default) DAC: powered down and timings are reset. Gain of Volume#1: fixed to 0dB Source of TVOUT: fixed to VCRIN Source of VCROUT: fixed to TVIN Source of MONOOUT: fixed to VCRIN Source of TVVOUT: fixed to VCRVIN (or Hi-Z) Source of TVRC: fixed to VCRRC (or Hi-Z) Source of TVG: fixed to VCRG (or Hi-Z) Source of TVB: fixed to VCRB (or Hi-Z) Source of TVFB: fixed to VCRFB (or Hi-Z) Source of TVSB: fixed to VCRSB Source of VCRVOUT: fixed to TVVIN (or Hi-Z) Source of VCRC: fixed to Hi-Z or VSS (controlled by CIO bit) MUTE: Audio output control 0: Normal operation 1: All Audio outputs to GND (default) DAPD: DAC power down control 0: Normal operation (default). 1: DAC power down. When DAPD bit = "1", the soft transition for volume does not work. AUTO: Auto startup bit 0: Auto startup disable (Manual startup). 1: Auto startup enable (default). When the SBIO1bit = "1"(default= "0"), the change of AUTO bit may cause a "L" pulse on INT pin. DIF1-0: Audio data interface format control 00: 16bit LSB Justified 01: 18bit LSB Justified 10: 24bit MSB Justified 11: 24bit I2S Compatible (default) DEM1-0: De-emphasis Response Control 00: 44.1kHz 01: off (default) 10: 48kHz 11: 32kHz
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ASAHI KASEI
[AK4706]
Addr 01H
Register Name Switch R/W default
D7 VMUTE 1
D6
0
D5 VCR1 0
D4 VCR0 1 R/W
D3
MONO
D2
VOL
D1 TV1 0
D0 TV0 1
0
0
1
TV1-0: TVOUTL/R pins source switch 00: DAC 01: VCRINL/R pins (default) 10: MUTE 11: (Reserved) VOL: MONOOUT pin source switch 0: Bypass the volume (fixed to DAC out) 1: Through the volume (default) MONO: Mono select for TVOUTL/R pins 0: Stereo. (default) 1: Mono. (L+R)/2 VCR1-0: VCROUTL/R pins source switch 00: DAC 01: TVINL/R pins (default) 10: MUTE 11: Volume #1 output VMUTE: Mute switch for volume #1 0: Normal operation 1: Mute the volume #1 (default)
Addr 02H
Register Name Main volume R/W Default
D7 0 0
D6 0 0
D5 L5 0
D4 L4 R/W 1
D3 L3 1
D2 L2 1
D1 L1 1
D0 L0 1
L5-0: Volume #1 control Those registers control both Lch and Rch of Volume #1. 111111 to 100011: (Reserved) 100010: Volume gain = +6dB 100001: Volume gain = +4dB 100000: Volume gain = +2dB 011111: Volume gain = +0dB (default) 011110: Volume gain = -2dB ... 000011: Volume gain = -56dB 000010: Volume gain = -58dB 000001: Volume gain = -60dB 000000: Volume gain = Mute
MS0507-E-00 - 43 -
2006/05
ASAHI KASEI
[AK4706]
Addr 03H
Register Name Zerocross R/W Default
D7 0 0
D6
VMONO 0
D5 1 1
D4 DVOL1 R/W 0
D3 DVOL0 0
D2 MOD 1
D1 MDT1 1
D0 MDT0 1
MDT1-0: The control of volume transition time (typ) 00: 256/fs 01: 512/fs 10: 1024/fs 11: 2048/fs (default) MOD: Soft transition enable for volume #1 control 0: Disable. The volume value changes immediately without soft transition. 1: Enable (default) The volume value changes with soft transition. This function is disabled when STBY bit or DAPD bit = "1". DVOL1-0: Volume #0/Volume #2 control. Refer the Table 10 and Table 11 VMONO: Mono select for VCROUTL/R pins 0: Stereo. (default) 1: Mono. (L+R)/2
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2006/05
ASAHI KASEI
[AK4706]
Addr 04H
Register Name Video switch R/W Default
D7 VRF1 1
D6 VRF0 0
D5 VVCR2 0
D4 VVCR1 1 R/W
D3 VVCR0 1
D2 VTV2 1
D1 VTV1 0
D0 VTV0 0
VTV2-0: Selector for TV video output Refer the Table 14. VVCR2-0: Selector for VCR video output Refer the Table 15 VRF1-0: Selector for RFV pin output Refer the Table 16. Addr 05H Register Name
Output enable
D7
CIO
D6
TVFB 0
D5
VCRC
D4
VCRV
D3
TVB
D2
TVG
D1
TVR
D0
TVV
R/W Default
R/W 0 0 0 0 0 0 0
TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control VCRV: VCRVOUT output control VCRC: VCRC output control (refer the Table 17) TVFB: TVFB output control 0: Hi-Z (default) 1: Active. When the CIO pin = "1", the VCRC pin is connected to GND even if VCRC= "0". When the CIO pin = "0", the VCRC pin follows the setting of VCRC bit. CIO: VCRC pin I/O control Refer the Table 17.
MS0507-E-00 - 45 -
2006/05
ASAHI KASEI
[AK4706]
Addr 06H
Register Name Video volume R/W Default
D7
CLAMPB
D6
VCLP1 0
D5
VCLP0
D4
CLAMP2
D3
CLAMP1
D2
CLAMP0
D1
VVOL1
D0
VVOL0
R/W 0 0 0 0 1 0 0
VVOL1-0: RGB video gain control 00: +6dB (default) 01: +7.2dB 10: +8.2dB 11: +9.1dB CLAMPB, CLAMP2-0: Clamp control. Refer the Table 19, Table 20 and Table 21. VCLP1-0: DC restore source control 00: ENCV pin (default) 01: ENCY pin 10: VCRVIN pin 11: (Reserved) When the AUTO bit = "1", the source is fixed to VCRVIN pin. Addr 07H Register Name S/F Blanking R/W Default D7 SBIO1 0 D6 SBIO0
0
D5 SBV1 0
D4 SBV0 R/W 0
D3 SBT1 0
D2 SBT0 0
D1 FB1 0
D0 FB0 0
FB1-0: TV Fast Blanking output control (for TVFB pin) 00: 0V (default) 01: 4V 10: follow VCR FB input (4V/0V) 11: (Reserved) SBT1-0: TV Slow Blanking output control (for TVSB pin. Load resistance is min.10kohm.) 00: <2V (default) 01: 5V to 7V 10: (Reserved) 11: 10V< SBV1-0: VCR Slow Blanking output control (for VCRSB pin. Load resistance is min.10kohm) 00: <2V (default) 01: 5V to 7V 10: (Reserved) 11: 10V< SBIO1-0: TV/VCR Slow Blanking I/O control (refer the Table 28) Addr 08H Register Name Monitor R/W Default D7 0 0 D6 0
0
D5 FVCR1 0
D4 TVMON 0 READ
D3 VCMON 0
D2 FVCR0 0
D1 SVCR1 0
D0 SVCR0 0
SVCR1-0, FVCR1-0: VCR fast blanking/slow blanking monitor Refer Table 29, Table 30. VCMON, TVMON: VCR/TV video input monitor Refer Table 31.
MS0507-E-00 - 46 -
2006/05
ASAHI KASEI
[AK4706]
Addr
09H
Register Name
Monitor mask
D7
MCOMN
D6
0 0
D5
0
D4
MTV
D3
MVC
D2
MFVCR
D1
MSVCR
D0
0
R/W default
R/W 0 0 0 1 0 0 0
MSVCR: SVCR1-0 Monitor mask. 0: The INT pin reflects the change of SVCR1-0 bits. (default) 1: The INT pin does not reflect the change of SVCR1-0 bit. MFVCR: FVCR Monitor mask. 0: The INT pin reflects the change of MFVCR bit. (default) 1: The INT pin does not reflect the change of MFVCR bit. MVC, MTV: VCR/TV monitor mask Refer the Table 32, Table 33.
MCOMN: Monitor mask option
Refer Table 31.
Addr 0AH
Register Name HD switch R/W default
D7 HDCP1 0
D6 HDCP0 0
D5 HDAPW
0
D4 SDC 0 R/W
D3 VCLP2 0
D2 0 0
D1 HDSW1 1
D0 HDSW0 1
HDSW1-0, HDCP1-0: HD video switch. Refer Table 23. HDAPW: auto startup bit (HD Video output) 1: Auto startup enable. 0: Auto startup disable (Manual startup: default). SDC: SCART-S1/S2 DC Control Refer Table 25, Table 26 Table 29 and Table 30. VCLP2: DC restore source control Refer Table 22 Addr 0BH Register Name HD filter R/W default D7 0 0 D6 0
0
D5 FLPR1 0
D4 FLPR0 0 R/W
D3 FLPB1 0
D2 FLPB0 0
D1 FLY1 0
D0 FLY0 0
FLY1-0, FLPB1-0, FLPR1-0: HD Video Filter Control Refer Table 24.
MS0507-E-00 - 47 -
2006/05
ASAHI KASEI
[AK4706]
SYSTEM DESIGN
Video 5V Audio 5V
10k
RF Modulator
0.1u
+ 10u 0.1u
+ 10u
+
10u 0.1u
VVSS3 63
NC 62
VVD4 61
NC 60
VVSS4 59
PDN 58
SDA 57
SCL 56
LRCK 55
SDTI 54
BICK 53
MCLK 52
VD2 51
VD1 50
VSS2 49
NC 64
Y/G out Pr/R out Pb/B out
75 75 75
1 HDY 2 HDPR 3 HDPB 4 VVD3 75 75 75 75 5 RFV 6 VCRVOUT 7 TVFB 8 VCRC 9 VVSS2 10 TVVOUT 11 VVD2 75 12 TVRC 75 13 TVG 75 14 TVB
0.1u VSS1 48
10u
10u 75 +
0.1u
AK4706
Video 5V
Micro controller
15 VVSS1 28 VCRVIN 23 ENCRC 30 VCRRC 19 ENCPR 20 ENCPB 29 VCRFB 18 ENCY2 27 TVVIN 22 ENCG 16 REFI 10k + 17 VVD1 24 ENCC 21 ENCB 25 ENCV 26 ENCY
+ PVCOM 47 0.1u 10u + DVCOM 46 10u + 0.1u VP 45 + 10u 300 MONOOUT 44 + 10u TVOUTL 43 220k + 10u TVOUTR 42 220k + 10u VCROUTL 41 220k + 10u VCROUTR 40 220k 300 0.1u TVINL 39 300 0.1u TVINR 38 300 0.1u VCRINL 37 300 0.1u VCRINR 36 400 TVSB 35 400 VCRSB 34 INT 33 31 VCRG 32 VCRB
Analog 12V
300 300 300 300
MPEG decoder
0.1u
10u
75
75
75
75
75
75
75
75
75
75
75
75
75
Digital Ground
Analog Ground
Figure 19. Typical Connection Diagram
MS0507-E-00 - 48 -
75
2006/05
VCR SCART
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
VIDEO encoder
0.1u
TV SCART
ASAHI KASEI
[AK4706]
Grounding and Power Supply Decoupling
VD1-2, VP, VVD1-4, VSS1-2 and VVSS1-4 should be supplied from analog supply unit with low impedance and be separated from system digital supply. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. The 0.1F ceramic capacitors should be placed as near to VD (VD1-2, VP, VVD1-4) as possible.
Voltage Reference
DVCOM and PVCOM are signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current may be drawn from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to avoid unwanted coupling into the AK4706.
Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms (typ@VD1=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio pass band. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is 5.6V(typ.) for 000000H (@24bit). The DC voltage on analog outputs are eliminated by AC coupling.
REFI pin
The REFI pin is video current reference pin. This pin should be connected to VVD1 through a 10k1% resistor externally as shown in the Figure 20. No load current may be drawn from this pin. All signals, especially clocks, should be kept away from this pin in order to avoid unwanted coupling.
AK4706
VVD1 R=10k1% REFI
Figure 20. REFI pin
MS0507-E-00 - 49 -
2006/05
ASAHI KASEI
[AK4706]
External Circuit Example
Analog Audio Input pin
300ohm TVINL/R VCRINL/R DACL/R
(Cable)
0.47F
Analog Audio Output pin
MONOOUT TVOUTL/R VCROUTL/R
10F
300ohm
(Cable)
Total > 4.5kohm
Analog Video Input pin
(Cable) 75ohm ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB, ENCPR, ENCY2, ENCPB
75ohm
0.1F
Analog Video Output pin
TVVOUT, TVRC TVG, TVR, RFV VCRVOUT, VCRC, HDPR, HDY, HDPB max 15pF 75ohm
(Cable) max 400pF 75ohm
MS0507-E-00 - 50 -
2006/05
ASAHI KASEI
[AK4706]
Slow Blanking pin (SDC bit = "0")
TVSB VCRSB 400ohm
(max 500ohm)
(Cable) max 3nF (with 400ohm) min: 10k ohm
Fast Blanking Input pin (SDC bit = "0")
VCRFB 75ohm (Cable) 75ohm
Fast Blanking Output pin (SDC bit = "0")
75ohm TVFB (Cable) 75ohm
Fast Blanking Output pin (SDC bit = "0")
TVFB TVSB
10k +/-3kohm
(Cable) Min: 100kohm
MS0507-E-00 - 51 -
2006/05
ASAHI KASEI
[AK4706]
PACKAGE
64p n LQ ( Un mm i FP it: )
12 00 3 . . 1 70m . ax 0 100 10 . . 1 40 .
33 32
10 0 .
48 49
64 1 16
17
12. 00. 3
0. 5
0 170 05 . . 0 10 M . 10 .
0 210 05 . .
0 ~10
0 450 2 . . 0 10 .
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0507-E-00 - 52 -
2006/05
ASAHI KASEI
[AK4706]
MARKING
AK4706VQ XXXXXXX
1
AKM
XXXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD) 06/05/09 Revision 00 Reason First Edition Page Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0507-E-00 - 53 -
2006/05

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